1. Field of the Invention
The invention relates generally to conductor contacts within semiconductor and other microelectronic structures. More particularly, the invention typically relates to conductor contacts with enhanced reliability within semiconductor structures, such as interconnect structures.
2. Description of the Related Art
Microelectronics fabrication typically provides for forming microelectronic devices within or upon a substrate. The devices may include semiconductor (i.e., typically active) devices as well as non-semiconductor (i.e., typically passive) devices. The devices are electrically connected and interconnected with patterned conductor layers that are embedded with one or more dielectric layers. These dielectric layers including the embedded conductor features are often referred to in the art as interconnect structures.
Microelectronic circuit performance is often determined not only by device performance characteristics, but also loss factors associated with patterned conductor wiring layers that provide power and signal connections to microelectronic devices. Loss factors, such as resistive losses, often occur at contact regions where patterned conductor layers connect directly to devices, or to each other. To reduce such resistive losses, patterned conductor layers routinely comprise copper materials that are formed using damascene methods, and in particular dual damascene methods.
Dual damascene methods provide for forming a blanket dielectric layer to cover a conductor contact region within a substrate. A via and a contiguous trench are formed into the blanket dielectric layer to provide a point of electrical contact to the conductor contact region. A blanket conductor is formed into the via and the contiguous trench. The structure is planarized to yield a contiguous patterned conductor interconnect and stud layer. Thus, at least one resistive interface between a conductor stud layer and a conductor interconnect layer is eliminated by using a dual damascene method, in comparison with other methods that may be used for forming patterned conductor layers within microelectronic circuits.
Various damascene methods, and permutations thereof, are known in the semiconductor and microelectronic fabrication arts. For example, Tsai et al., in U.S. Pat. No. 6,562,725, teaches a dual damascene method and a dual damascene structure that provide for enhanced manufacturability. The method and the structure use: (1) a first etch stop layer (covering a contact region) comprising one of a silicon carbide material and a nitrogenated silicon carbide material; and (2) a second etch stop layer (interposed between a first dielectric layer and a second dielectric layer) comprising the other of the silicon carbide material and the nitrogenated silicon carbide material.
Conductor contact resistance losses are clearly not totally eliminated by using dual damascene methods and dual damascene structures within semiconductor and microelectronic circuits. Thus, additional methods and structures are clearly desirable to provide conductor contacts with low contact resistance and enhanced reliability.